MC74HC4053 |
RFQ for MC74HC4053 Required Field |
 |
| Technical/Catalog Information | MC74HC4053AD |
| Vendor | ON Semiconductor |
| Category | Integrated Circuits (ICs) |
| Type | Multiplexer/Demultiplexer |
| Voltage Supply Source | Single, Dual Supply |
| Voltage - Supply, Single/Dual (±) | ±2 V ~ 6 V, 2 V ~ 12 V |
| Circuit | 3 x 2:1 |
| On-State Resistance | 100 Ohm |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (3.9mm Width) |
| Packaging | Tube |
| Current - Supply | 40A |
| Operating Temperature | -55°C ~ 125°C |
| Function | Multiplexer/Demultiplexer |
| Drawing Number | * |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | MC74HC4053AD MC74HC4053AD MC74HC4053ADOS ND MC74HC4053ADOSND MC74HC4053ADOS |
| Product | Manufacturers | Pack | D/C |
| MC74HC4053 | - | 97+ | SOP3.9 |
The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE).
The HC4051, HC4052 and HC4053 are identical in pinout to the metalgate MC14051B, MC14052B and MC14053B. The ChannelSelect inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.
The ChannelSelect and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs.
These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metalgate CMOS analog switches.
For multiplexers/demultiplexers with channelselect latches, see HC4351, HC4352 and HC4353.
Typical Application |
Features |
| The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic highGND = 0V = logic lowThe maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analogvoltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peaktopeak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch.Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: | • Fast Switching and Propagation Speeds• Low Crosstalk Between Switches• Diode Protection on All Inputs/Outputs• Analog Power Supply Range (VCC VEE) = 2.0 to 12.0 V• Digital (Control) Power Supply Range (VCC GND) = 2.0 to 6.0 V• Improved Linearity and Lower ON Resistance Than MetalGate Counterparts• Low Noise• In Compliance With the Requirements of JEDEC Standard No. 7A• Chip Complexity: HC4051 - 184 FETs or 46 Equivalent Gates HC4052 - 168 FETs or 42 Equivalent Gates HC4053 - 156 FETs or 39 Equivalent Gates |
|
Symbol |
Parameter |
Value |
Unit |
|
VCC |
Positive DC Supply Voltage (Referenced to GND) (Referenced to GND) |
0.5 to +7.0 0.5 to +14.0 |
V |
|
VEE |
Negative Dc Supply Voltage (Referenced to GND) |
7.0 to VCC +0.5 |
V |
|
VIS |
Anaolg Input Voltage |
VEE 0.5 to VCC + 0.5 |
V |
|
Iin |
Digital Input (Referenced to GND) |
0.5 to VCC + 0.5 |
V |
|
I |
DC Curent,Intl or Out of Any Pin |
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